Model-driven development methodology applied to real-time MEG signal pre-processing system design

The thesis is a multidisciplinary work that uses model-based systems engineering (MBSE) for developing real-time magnetoencephalography (MEG) signal processing.</br> In magnetoencephalography signal processing, biological artifacts in particular overtop the signal of interest by orders of magnitude and must be removed during signal processing from the measured signals to achieve a high quality reconstruction with minimized error contribution. This is a computational extremely demanding challenge as standard MEG systems include 248 and more channels in parallel. In this work, the automated real-time artifact rejection based on the recently presented method “ocular and cardiac artifact rejection for real-time analysis in MEG” (OCARTA) has been implemented by a MBSE approach and successfully verified on a Virtex-6 FPGA.</br> The requirement-driven, model-based development methodology (RDD & MBD) provides a high-level environment and efficiently handles the complexity of computation and control systems. The applied development methodology focuses on the use of Systems Modeling Language (SysML) to define high-level model-based design descriptions for later implementation in heterogeneous hardware/software systems. In order to demonstrate the capability of the proposed approach, it was applied and further developed to the implementation of a real-time artifact rejection unit in MEG signal processing.</br> The work of this thesis is embedded in the Jülich Research Center (Forschungszentrum Jülich GmbH, Germany) MEG-RT 2.0 project, which aims at developing an MEG real-time signal-processing device to be used as an add-on to existing MEG systems, thus enabling, for example, neuro-feedback applications. The system model of the real-time MEG signal processing chain developed here and the verified real-time artifact rejection implementation is a first and essential component of the Jülich Research Center MEG-RT 2.0 project.</br>



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