Schaltungsbezogene Modellierung der Ausbeute und des Ausfallrisikos mikroelektronischer Schaltkreise unter Berücksichtigung defektinduzierter Ausfallmechanismen
A procedure for yield prediction and reliability estimation for microlectronic circuit manufacturing was developed in this thesis. Therefore the interaction between defects distributed randomly and chip layout structures was investigated mainly. At first a new method for the optical defect measurement has been introduced considering the real defect outline which is unavoidable to extract the correct defect size distribution. The simulation tool CALYPSO was created to detect the sensitivity of the layout on defects of various types and sizes. The code benefits from a novel combination of well known simulation principles to reach a very high speed of the numerical runs. Not only yield relevant defects can be considered but latent and build-in reliability defects leading to lifetime shortening too. For this two additional special modules have been implemented. So CALYPSO can not only predict the reachable yield of any microelectronic circuit manufacturing but can also be used for IC lifetime estimation.