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Dissertation angenommen durch: Universität Duisburg-Essen, Campus
Duisburg, Fakultät für Ingenieurwissenschaften, Abteilung
Elektrotechnik und Informationstechnik, 2004-08-06
BetreuerIn: Prof. Dr.-Ing. Axel Hunger ,
Universität Duisburg-Essen, Campus Duisburg, Fakultät für
Ingenieurwissenschaften, Abteilung Elektrotechnik und
Informationstechnik
GutachterIn: Prof. Dr.-Ing Axel Hunger , Universität
Duisburg-Essen, Campus Duisburg, Fakultät für Ingenieurwissenschaften,
Abteilung Elektrotechnik und Informationstechnik
GutachterIn: Prof. Dr.-Ing. Bernd Straube , Fraunhofer Institut Integrierte Schaltungen, Dresden, Aussenstelle Entwurfsautomatisierung
Schlüsselwörter in Englisch: analog test, testability analysis, controllability, observability, measurement selection, pole zero analysis, analog circuits
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Abstrakt in Englisch
Testability analysis for analog circuits provides valuable information
for designers and test engineers. Such information includes a number of
testable and nontestable elements of a circuit, ambiguity groups, and
nodes to be tested. This information is useful for solving the fault
diagnosis problem.
In order to verify the functionality of analog circuits, a large number
of specifications have to be checked. However, checking all circuit
specifications can result in prohibitive testing times on expensive
automated test equipment. Therefore, the test engineer has to select a
finite subset of specifications to be measured. This subset of
specifications must result in reducing the test time and guaranteeing
that no faulty chips are shipped.
This research develops a novel methodology for testability analysis of
linear analog circuits based on pole-zero analysis and on pole-zero
sensitivity analysis. Based on this methodology, a new interpretation
of ambiguity groups is provided relying on the circuit theory. The
testability analysis methodology can be employed as a guideline for
constructing fault diagnosis equations and for selecting the test
nodes.
We have also proposed an algorithm for selecting specifications that
need to be measured. The element testability concept will be
introduced. This concept provides the degree of difficulty in testing
circuit elements. The value of the element testability can easily be
obtained using the pole sensitivities. Then, specifications which need
to be measured can be selected based on this concept. Consequently, the
selected measurements can be utilized for reducing the test time
without sacrificing the fault coverage and maximizing the information
for fault diagnosis.
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